Friday, December 1, 2017
VERILOG HDL(15EC53) QUESTION BANK (Module 1 to Module 5)
VERILOG HDL(15EC53) QUESTION BANK (Module 1 to Module 5) including model paper and Exercise examples
Sunday, November 26, 2017
VERILOG HDL(15EC53) MODULE 5 NOTES
VERILOG HDL(15EC53) MODULE 5
Introduction to VHDL
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions.
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes.
Introduction to VHDL
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions.
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes.
Sunday, November 12, 2017
VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS
VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS
VERILOG HDL(15EC53) MODULE 4 NOTES
VERILOG HDL(15EC53) MODULE 4 NOTES
SYLLABUS: Behavioral Modeling Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.
Sunday, October 15, 2017
VERILOG HDL(15EC53) MODULE 3 NOTES
Verilog HDL Module 3 .
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators, operands, operator types.
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators, operands, operator types.
Tuesday, September 12, 2017
MODULE 2 QUESTION BANK (15EC53)
Module 2 Question Bank (15EC53)
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